Integrated circuits or electronic chips are ubiquitous, being contained in many electronic devices used by a person during a typical day, such as in cellular telephones, personal computers, automobiles, and even common household appliances like toasters. A chip includes a semiconductor die, which is made of semiconductor material such as silicon, and in which desired electronic circuitry is formed. For example, a memory chip is a chip containing a die in which electronic circuitry is formed for storing and retrieving data. A chip also includes a package that houses the die and includes pins that provide for electrical interconnection of the chip to external electronic components. Various different types of packages are utilized for chips, with the specific type of package being determined by numerous factors such as required heat dissipation, the physical size of the chip, and the number of interconnections needed from the die to external electronic components. Common packages for chips include single in-line packages (SIPs), dual in-line packages (DIPs), plastic leaded chip carriers (PLCC), Thin Small Outline Packages (TSOPs), pin-grid arrays (PGAs), ball-grid arrays (BGAs), and quad flat packs (QFPs).
In some situations, more than one die is housed in a given package to form what is commonly referred to as a “system in a package” (SIP) device or simply a SIP. The two or more die in this situation must be electrically interconnected, and depending on the type of package this interconnection may present difficulties. These difficulties often occur when using any type of package including a lead frame, such as the DIP, PLCC, TSOP, and QFP packages previously mentioned. For example, a quad-flat pack (QFP) is a package having pins or external leads that project from all four sides of the package. QFP packages are relatively cheap and also are relatively thin (i.e., have a small height) compared to other types of packages, and accordingly may be utilized where cost and height of the package are of concern. A QFP package includes a lead frame and the physical structure of the lead frame and overall QFP package makes the interconnection of multiple dies in such a package problematic.
FIG. 1 is a simplified top view of a portion of a chip including a conventional QFP package containing a lead frame 100. The lead frame 100 includes a die paddle 102 on which two die 104 and 106 are mounted. For example, the die 104 could be a dynamic random access memory (DRAM) and the die 106 a memory controller that are being combined to form a SIP. The die paddle 102 is supported by four support arms 108 (commonly called tie bars) attached to respective corners of the die paddle. Arranged around the periphery of the die paddle 102 are a number of bond fingers 110, several of which are shown along the top, bottom, left, and right edges of the paddle. These bond fingers 110 typically extend from all four sides of the QFP package to form the external leads of the package and are also coupled or connected through respective bonding wires 112 to corresponding bond pads 114 on one of the dies 104 and 106. Each bond finger 110 functions to route a respective electrical signal to or from the dies 104 and 106. All signals required for operation of the dies 104 and 106 are routed to and from the dies either through the bond fingers 110, such as ground signals, supply voltages, controls signals, data signals, address signals, and so on, or between each die through bond wires 112. The specific type and number of such signals depends on the types of the dies 104 and 106.
The die paddle 102, bond fingers 110, bonding wires 112, and bond pads 114 are all formed from electrically conductive material, such as a metal, as will be appreciated by those skilled in the art. The illustrated bond pads 114 on each of the dies 104 and 106 merely serve to indicate that each die includes such bond pads and the number and arrangement of such bond pads will of course vary for different types of dies. The die paddle 102 is typically metal and is typically utilized as a ground plane, meaning that the paddle is coupled through bonding wires 112 to bond fingers 110 that receive a ground signal GND. A bond finger 110a, for example, positioned along the top left edge of the die paddle 102 receives the ground signal GND and is coupled through a respective bonding wire 112a to the die paddle 102. Any bond pads 114 on the dies 104 and 106 that are to be coupled to ground are then simply “down bonded” to the die paddle 102, meaning such bond pads are coupled directly to the die paddle via a corresponding bonding wire 112. Several examples of down bonded ground wires are shown in FIG. 1, such as the bond pad 114a formed along the top edge of the die 106 that is down bonded to the die paddle 102 through the bonding wire 112b. 
The dies 104 and 106 are interconnected through bond pads 114b positioned along an inner edge of the die 104 and bond pads 114c positioned along an inner edge of the die 106. The interconnection of these bond pads 114b and 114c through bonding wires 112 is simple when the bond pads on the dies 104 and 106 line up, which is the case in the example illustrated in FIG. 1. More specifically, the uppermost bond pad 114b is connected to the uppermost bond pad 114c through an uppermost bonding wire 112, with the second from the top bond pad 114b being connected to the second from the top bond pad 114c through a bonding wire 112, and so on for pairs of bond pads 114b and 114c from top to bottom.
The structure of a QFP package, along with other types of packages including lead frames, requires that bonding wires 112 be used to directly interconnect the bond pads 114 to the bond fingers 110 as required. The same is true of the interconnection of the bond pads 114b along the inner edge of die 104 and the bond pads 114c along the inner edge of die 106. This is in contrast to other types of packages such as ball grid arrays where there is an underlying substrate on which the two die 104 and 106 are mounted. This substrate functions like a miniature circuit board and simplifies the routing of signals between the bond fingers 110 and the bond pads 114 as well as signals between the two dies 104 and 106.
When the bond pads 114b along the inner edge of die 104 do not line up as required with bond pads 114c along the inner edge of die 106, a problem arises in properly electrically interconnecting the two dies. This is true, for example, because short circuits may arise if the bonding wires 112 cross over one another in interconnecting the bond pads 114b and 114c or if bond pads on the two dies 104 and 106 that are to be interconnected are not located along the respective inner edges of the dies. Unless the two dies 104 and 106 have been originally designed for use in SIP applications, it is unlikely the bond pads 114b and 114c will line up as required.
One approach to ensuring the bond pads 114b and 114c line up as required is to alter the designs of the dies 104 and 106 so as to reposition the location of the bond pads along the inner edge of each die to be directly across from the corresponding bond pad on the other die. Ideally, however, it is desirable for the same dies 104 and 106 to be utilized whether the dies are being placed in a QFP package, a ball grid array package, or any other type of package. Repositioning the bond pads 114b and 114c that are located along the inner edges of the dies 104 and 106 may make the die unsuitable for use individually in other types of standard packages. Moreover, this redesign of dies 104 and 106 is relatively expensive and time consuming since it involves the cost of new mask layers used in the die fabrication process and the time it takes to fabricate new die.
Another approach for enabling the required electrical interconnection of the dies 104 and 106 is an interposer layer positioned under the dies. The interposer layer functions similar to the substrate previously described for a ball grid array to electrically interconnect required bond pads on the two dies 104 and 106. Once again, however, this approach is relatively expensive and therefore generally undesirable. Moreover, an interposer layer also increases the vertical height of the QFP package and thereby contravenes one major advantage of a QFP package, namely the small overall height of the QFP package. The same is true for the approach of stacking the two dies 104 and 106, which may not be practical if the size of the two dies are incompatible and also undesirably affects the heat dissipation and overall height of the QFP package.
Yet another approach for aligning bond pads 114b and 114c along the inner edges of the dies 104 and 106 is to relocate the pad locations using a redistribution layer (“RDL”) formed as an additive process on the top of one or both of the dies. As its name implies, such a redistribution layer redistributes or repositions the locations of underlying bond pads 114 on the dies 104 and 106. With this approach, the bond pads 114h and 114c along the inner edges of the dies 104 and 106 would be repositioned as required to enable proper interconnection of the two dies.
FIG. 2 is a simplified top view of a portion of a lead frame 200 including a die paddle 202 on which two dies 204 and 206 are mounted. A redistribution layer 208 is formed on the die 204 to provide relocated bond pads 210 along the inner edge of the die. These relocated bond pads 210 are properly aligned with corresponding bond pads 212 positioned along an inner edge of the die 206 such that bonding wires 214 may be used to electrically interconnect the bond pads on the two dies. The redistribution layer 208 includes a number of electrically conductive traces 216 that electrically interconnect the bond pads 210 along the inner edge of the die 204 to bond pads positioned along other edges of the die. For example, electrically conductive traces 216 in the redistribution layer 208 interconnect original bond pads 218 positioned along a bottom edge of the die 204 to corresponding bond pads 210 along the inner edge. Similarly, electrically conductive traces 216 interconnect original bond pads 220 along a top edge of the die 204 to corresponding bond pads 210 along the inner edge. The redistribution layer 208 includes numerous conductive traces 216, with only some of the traces being labeled in FIG. 2 in order to simplify the figure. The bond pads 218 and 220 are electrically interconnected through bonding wires 222 to bond fingers (not shown) as previously discussed with reference to FIG. 1.
While the use of the redistribution layer 208 for relocating the bond pads 218, 220 is less expensive and faster than modifying the dies 204 and 206 themselves, there are limitations to this approach. First, the redistribution layer 208 must be designed and physically formed on one or both the dies 204 and 206 to provide the required electrical interconnections. At present, the redistribution layer 208 is limited to a single layer structure, which limits the routing of the electrically conductive traces 216. This is true because the relocated bond pads 210 must be electrically interconnected through respective traces 216 to the required original pads 218 and 220. Depending on the number and order of the relocated bond pads 210, the conventional single layer redistribution layer 208 may not be able to provide all the required electrical interconnections. For example, if a bond pad 220 located along the upper-right edge of the die 204 needs to be connected to one of the relocated bond pads 210 near the bottom edge of the die, the routing of the required trace 216 could be difficult or impossible. As a result, the option of using the single layer redistribution layer 208 may not be available in some situations. Multilayer redistribution layers are not currently available for use in mass production SIPs and thus is not an option in commercial situations.
There is a need in QFP or other leadframe packages that include more than one die for simply, inexpensively, and reliably interconnecting all dies contained in the package.